(myvar and Myvar are different identifiers)
Following characters may be alphabetic, digit, underscore, or dollar sign. First character must be alphabetic or an underscore (_) Identifiers are used for module names, module instance names, and // Whitespace is a non-zero string of spaces, tabs, newlines, formfeeds. This is like C/C++, but unlike Fortran and VHDL. For example, My_Module and my_module are different. / Highlights of SystemVerilog lexical conventions: // // Identifiers (variable names, module names, etc.) are case sensitive. / Identifiers and Whitespace // :SV12: Chapter 5 // :BV3: Brown & Vranesic, Fundamentals of Digital Logic with Verilog, 3rd Ed. 299 595/ // This is for those already familiar with Verilog. / References // :SV17: IEEE 1800-2017 - The SystemVerilog Standard Vectors and other Packed Arrays, Unpacked Arrays / Contents // Identifiers and Whitespace / Objects and Data Types // Time-stamp:
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